1. Field of the Invention
The present invention relates to a semiconductor memory device using internal and external power voltages, and in particular to a method and a device for controlling the internal power voltage during a power-up period in the semiconductor memory device using the internal and the external power voltage.
2. Description of the Related Art
As the term implies, ‘power-up’ refers to an external power voltage that is provided to a semiconductor device upon a starting operation.
FIG. 1 is a block diagram illustrating a conventional IVC (Internal Voltage Converter) in a semiconductor memory device using internal power voltage Vint and external power voltage Vext. FIG. 2 is a graph illustrating the changing internal power voltage Vint and external power voltage Vext during a power-up period in a semiconductor memory device.
Referring to FIG. 1, the IVC (Internal Voltage Converter) 10 generates the internal power voltage Vint using the external power voltage Vext. A first voltage drop of the external power voltage Vext is caused by an RC input terminal 12 and a second voltage drop of the internal power voltage Vint is caused by an RC output terminal 14 coupled to an output of the IVC 10.
As illustrated in FIG. 2, the external power voltage Vext, which may be supplied from a pad of a semiconductor memory device, has a linear power-up slope during a power-up period. This linearity may be attributed to the external power voltage Vext being supplied by a virtually unlimited power source.
This is not the case, however, for the internal power voltage Vint, which is supplied from circuitry of the IVC. This circuitry embodies elements that result in a time-dependent transient voltage that lags behind that of Vext during a power-up period. This can be seen as Vint lagging behind Vext in FIG. 2 during the period A.